(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to fabricate a fin type field effect transistor (FINFET) device on a semiconductor substrate.
(2) Description of Prior Art
Micro-miniaturization, the ability to fabricate semiconductor devices comprised with sub-micron features, has allowed the performance of devices comprised with the sub-micron features to be increased. In addition the use of sub-micron features has allowed the attainment of smaller semiconductor chips to be realized, still providing device density equal to, or greater than, counterpart semiconductor chips formed with larger features, therefore allowing a greater number of semiconductor chips to be obtained from a specific size starting silicon wafer thus reducing the processing costs for a specific semiconductor chip. However as device features shrink specific parameters such as short channel effects, punch through, and leakage currents become more prevalent for devices formed with sub-micron features than for counterparts formed with larger features. The ability to fabricate a FINFET type device entirely in a silicon in insulator (SOI) layer, has allowed miniaturization of device features to be successfully accomplished with less risk of the yield degrading phenomena such as short channel effects, punch through leakages, and leakage current, when compared to counterpart devices formed in a semiconductor substrate. In addition the FINFET device, formed on an insulator layer, results in less junction capacitance, thus increased performance, when compared to the above counterpart devices formed in the semiconductor material.
The use of FINFET type devices however has mainly been applied to a single type metal oxide semiconductor field effect transistor (MOSFET), device, either an N channel (NMOS), device, or a P channel (PMOS), device. The ability to fabricate a complimentary metal oxide semiconductor (CMOS), device, comprised with both NMOS and PMOS devices, has been difficult to achieve for FINFET type devices. This invention will describe a novel process sequence in which the attractive advantages of FINFET devices can be realized for both NMOS and PMOS elements, formed in the same SOI layer. In addition this invention will describe additional process sequences allowing source/drain, as well as gate resistances for the FINFET device, to be reduced, thus providing additional performance enhancements. Prior art, such as Wu, in U.S. Pat. No. 6,010,934, Wu, in U.S. Pat. No. 6,117,711, and Muller et al, in U.S. Pat. No. 6,252,284 B1, describe methods of forming FIN type devices, however none of these prior arts describe the novel process sequence of this present invention in which a NMOS and a PMOS FINFET device are formed in the same SOI layer.
It is an object of this invention to fabricate both an NMOS FINFET, and a PMOS FINFET device in the same SOI layer.
It is another object of this invention to dope source/drain regions of both the NMOS and PMOS elements of the CMOS FINFET device, via out diffusion from overlying doped insulator layers.
It is still another object of this invention to decrease FINFET source/drain resistance via use of a selectively deposited, overlying metal layer.
It is still yet another object of this invention to reduce FINFET gate resistance via use of dummy silicon fins, or via a reduction in spacing between the silicon fins.
In accordance with the present invention a method of forming both NMOS and PMOS FINFET devices in the same SOI layer, is described. Fin type structures used to accommodate a subsequent NMOS FINFET device and a subsequent PMOS device, are formed in an SOI layer, each comprised with an overlying insulator shape. After formation of a gate insulator layer on the sides of the FIN type structures, a conductive gate structure is defined, normal in direction to, and traversing the FIN type structures. Insulator spacers are formed on the sides of the gate structure as well as on the sides of the insulator shapexe2x80x94FIN type structures. Removal of the insulator shapes expose top surfaces of SOI for the portions of FIN type structures not covered by the conductive gate structure. An N type doped insulator layer is formed overlying a first FIN type structure, to be used for the NMOS FINFET device, while a P type doped insulator layer is provided overlying the second FIN type structure to be used for the PMOS FINFET device. An anneal procedure results in an NMOS FINFET device, with the exposed portions of the first FIN type structure now an N type source/drain region, and results in a PMOS FINFET device, with the exposed portions of the second FIN type structure now a P type source/drain region. After removal of the doped insulator layers, selective metal deposition on the top surface of both N type, and P type source/drain regions is performed.
A second embodiment of this invention entails the use of dummy fin structures located between the NMOS and PMOS fin structures, allowing the deposition of the material used for the conductive gate to fill the spaces between the fin structures, thus reducing gate resistance when compared to counterparts in which the conductive gate material only contoured the fin type structures.